/* SPDX-License-Identifier: GPL-2.0+ */
// $Module: reg_G7_PINMUX_REG $
// $RegisterBank Version: v1.0.00 $
// $Author:  $
// $Date: Tue, 23 May 2023 09:41:19 PM $
//

//GEN REG ADDR/OFFSET/MASK
#define  G7_PINMUX_REG_REG_CLK_25M_OUT  0x0
#define  G7_PINMUX_REG_REG_PWR_ON  0x4
#define  G7_PINMUX_REG_REG_PWR_BUTTON1  0x8
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0  0xc
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1  0x10
#define  G7_PINMUX_REG_REG_PWR_SEQ1  0x14
#define  G7_PINMUX_REG_REG_PWR_SEQ2  0x18
#define  G7_PINMUX_REG_REG_PWR_SEQ3  0x1c
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA  0x20
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL  0x24
#define  G7_PINMUX_REG_REG_PWR_UART_TX  0x28
#define  G7_PINMUX_REG_REG_PWR_UART_RX  0x2c
#define  G7_PINMUX_REG_REG_PWR_GPIO0  0x30
#define  G7_PINMUX_REG_REG_PWR_GPIO1  0x34
#define  G7_PINMUX_REG_REG_PWR_GPIO2  0x38
#define  G7_PINMUX_REG_REG_PWR_GPIO3  0x3c
#define  G7_PINMUX_REG_REG_PWR_GPIO4  0x40
#define  G7_PINMUX_REG_REG_PWR_GPIO5  0x44
#define  G7_PINMUX_REG_REG_PWR_GPIO6  0x48
#define  G7_PINMUX_REG_REG_PWR_RSTN  0x4c
#define  G7_PINMUX_REG_REG_CLK_25M_SEL  0x50
#define  G7_PINMUX_REG_REG_PWR_XTAL  0x54
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_P_EN   0x0
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_PU_SEL   0x0
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_PIN_SEL_EN   0x0
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_DRI_SEL   0x0
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_SCT_EN   0x0
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_OEX_EN   0x0
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_ON_P_EN   0x4
#define  G7_PINMUX_REG_REG_PWR_ON_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_ON_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_ON_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_ON_PU_SEL   0x4
#define  G7_PINMUX_REG_REG_PWR_ON_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_ON_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_ON_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_ON_PIN_SEL_EN   0x4
#define  G7_PINMUX_REG_REG_PWR_ON_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_ON_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_ON_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_ON_DRI_SEL   0x4
#define  G7_PINMUX_REG_REG_PWR_ON_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_ON_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_ON_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_ON_SCT_EN   0x4
#define  G7_PINMUX_REG_REG_PWR_ON_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_ON_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_ON_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_ON_OEX_EN   0x4
#define  G7_PINMUX_REG_REG_PWR_ON_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_ON_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_ON_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_P_EN   0x8
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_PU_SEL   0x8
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_PIN_SEL_EN   0x8
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_DRI_SEL   0x8
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_SCT_EN   0x8
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_OEX_EN   0x8
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_BUTTON1_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_P_EN   0xc
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_PU_SEL   0xc
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_PIN_SEL_EN   0xc
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_DRI_SEL   0xc
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_SCT_EN   0xc
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_OEX_EN   0xc
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_WAKEUP0_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_P_EN   0x10
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_PU_SEL   0x10
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_PIN_SEL_EN   0x10
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_DRI_SEL   0x10
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_SCT_EN   0x10
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_OEX_EN   0x10
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_WAKEUP1_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ1_P_EN   0x14
#define  G7_PINMUX_REG_REG_PWR_SEQ1_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_SEQ1_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ1_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ1_PU_SEL   0x14
#define  G7_PINMUX_REG_REG_PWR_SEQ1_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_SEQ1_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_SEQ1_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ1_PIN_SEL_EN   0x14
#define  G7_PINMUX_REG_REG_PWR_SEQ1_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_SEQ1_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_SEQ1_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_SEQ1_DRI_SEL   0x14
#define  G7_PINMUX_REG_REG_PWR_SEQ1_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_SEQ1_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_SEQ1_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_SEQ1_SCT_EN   0x14
#define  G7_PINMUX_REG_REG_PWR_SEQ1_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_SEQ1_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_SEQ1_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ1_OEX_EN   0x14
#define  G7_PINMUX_REG_REG_PWR_SEQ1_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_SEQ1_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_SEQ1_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ2_P_EN   0x18
#define  G7_PINMUX_REG_REG_PWR_SEQ2_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_SEQ2_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ2_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ2_PU_SEL   0x18
#define  G7_PINMUX_REG_REG_PWR_SEQ2_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_SEQ2_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_SEQ2_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ2_PIN_SEL_EN   0x18
#define  G7_PINMUX_REG_REG_PWR_SEQ2_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_SEQ2_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_SEQ2_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_SEQ2_DRI_SEL   0x18
#define  G7_PINMUX_REG_REG_PWR_SEQ2_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_SEQ2_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_SEQ2_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_SEQ2_SCT_EN   0x18
#define  G7_PINMUX_REG_REG_PWR_SEQ2_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_SEQ2_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_SEQ2_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ2_OEX_EN   0x18
#define  G7_PINMUX_REG_REG_PWR_SEQ2_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_SEQ2_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_SEQ2_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ3_P_EN   0x1c
#define  G7_PINMUX_REG_REG_PWR_SEQ3_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_SEQ3_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ3_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ3_PU_SEL   0x1c
#define  G7_PINMUX_REG_REG_PWR_SEQ3_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_SEQ3_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_SEQ3_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ3_PIN_SEL_EN   0x1c
#define  G7_PINMUX_REG_REG_PWR_SEQ3_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_SEQ3_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_SEQ3_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_SEQ3_DRI_SEL   0x1c
#define  G7_PINMUX_REG_REG_PWR_SEQ3_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_SEQ3_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_SEQ3_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_SEQ3_SCT_EN   0x1c
#define  G7_PINMUX_REG_REG_PWR_SEQ3_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_SEQ3_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_SEQ3_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_SEQ3_OEX_EN   0x1c
#define  G7_PINMUX_REG_REG_PWR_SEQ3_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_SEQ3_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_SEQ3_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PU_EN   0x20
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PU_EN_OFFSET 2
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PU_EN_MASK   0x4
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PU_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PD_EN   0x20
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PD_EN_OFFSET 3
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PD_EN_MASK   0x8
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PD_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PIN_SEL_EN   0x20
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_DRI_SEL   0x20
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_SCT_EN   0x20
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_OEX_EN   0x20
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_IIC_SDA_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PU_EN   0x24
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PU_EN_OFFSET 2
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PU_EN_MASK   0x4
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PU_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PD_EN   0x24
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PD_EN_OFFSET 3
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PD_EN_MASK   0x8
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PD_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PIN_SEL_EN   0x24
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_DRI_SEL   0x24
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_SCT_EN   0x24
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_OEX_EN   0x24
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_IIC_SCL_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_UART_TX_P_EN   0x28
#define  G7_PINMUX_REG_REG_PWR_UART_TX_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_UART_TX_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_UART_TX_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_UART_TX_PU_SEL   0x28
#define  G7_PINMUX_REG_REG_PWR_UART_TX_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_UART_TX_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_UART_TX_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_UART_TX_PIN_SEL_EN   0x28
#define  G7_PINMUX_REG_REG_PWR_UART_TX_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_UART_TX_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_UART_TX_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_UART_TX_DRI_SEL   0x28
#define  G7_PINMUX_REG_REG_PWR_UART_TX_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_UART_TX_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_UART_TX_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_UART_TX_SCT_EN   0x28
#define  G7_PINMUX_REG_REG_PWR_UART_TX_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_UART_TX_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_UART_TX_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_UART_TX_OEX_EN   0x28
#define  G7_PINMUX_REG_REG_PWR_UART_TX_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_UART_TX_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_UART_TX_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_UART_RX_P_EN   0x2c
#define  G7_PINMUX_REG_REG_PWR_UART_RX_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_UART_RX_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_UART_RX_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_UART_RX_PU_SEL   0x2c
#define  G7_PINMUX_REG_REG_PWR_UART_RX_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_UART_RX_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_UART_RX_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_UART_RX_PIN_SEL_EN   0x2c
#define  G7_PINMUX_REG_REG_PWR_UART_RX_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_UART_RX_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_UART_RX_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_UART_RX_DRI_SEL   0x2c
#define  G7_PINMUX_REG_REG_PWR_UART_RX_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_UART_RX_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_UART_RX_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_UART_RX_SCT_EN   0x2c
#define  G7_PINMUX_REG_REG_PWR_UART_RX_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_UART_RX_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_UART_RX_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_UART_RX_OEX_EN   0x2c
#define  G7_PINMUX_REG_REG_PWR_UART_RX_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_UART_RX_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_UART_RX_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO0_P_EN   0x30
#define  G7_PINMUX_REG_REG_PWR_GPIO0_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_GPIO0_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO0_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO0_PU_SEL   0x30
#define  G7_PINMUX_REG_REG_PWR_GPIO0_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_GPIO0_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_GPIO0_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO0_PIN_SEL_EN   0x30
#define  G7_PINMUX_REG_REG_PWR_GPIO0_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_GPIO0_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_GPIO0_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO0_DRI_SEL   0x30
#define  G7_PINMUX_REG_REG_PWR_GPIO0_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_GPIO0_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_GPIO0_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO0_SCT_EN   0x30
#define  G7_PINMUX_REG_REG_PWR_GPIO0_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_GPIO0_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_GPIO0_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO0_OEX_EN   0x30
#define  G7_PINMUX_REG_REG_PWR_GPIO0_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_GPIO0_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_GPIO0_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO0_IE   0x30
#define  G7_PINMUX_REG_REG_PWR_GPIO0_IE_OFFSET 14
#define  G7_PINMUX_REG_REG_PWR_GPIO0_IE_MASK   0x4000
#define  G7_PINMUX_REG_REG_PWR_GPIO0_IE_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO1_P_EN   0x34
#define  G7_PINMUX_REG_REG_PWR_GPIO1_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_GPIO1_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO1_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO1_PU_SEL   0x34
#define  G7_PINMUX_REG_REG_PWR_GPIO1_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_GPIO1_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_GPIO1_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO1_PIN_SEL_EN   0x34
#define  G7_PINMUX_REG_REG_PWR_GPIO1_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_GPIO1_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_GPIO1_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO1_DRI_SEL   0x34
#define  G7_PINMUX_REG_REG_PWR_GPIO1_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_GPIO1_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_GPIO1_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO1_SCT_EN   0x34
#define  G7_PINMUX_REG_REG_PWR_GPIO1_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_GPIO1_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_GPIO1_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO1_OEX_EN   0x34
#define  G7_PINMUX_REG_REG_PWR_GPIO1_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_GPIO1_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_GPIO1_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO1_IE   0x34
#define  G7_PINMUX_REG_REG_PWR_GPIO1_IE_OFFSET 14
#define  G7_PINMUX_REG_REG_PWR_GPIO1_IE_MASK   0x4000
#define  G7_PINMUX_REG_REG_PWR_GPIO1_IE_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO2_P_EN   0x38
#define  G7_PINMUX_REG_REG_PWR_GPIO2_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_GPIO2_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO2_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO2_PU_SEL   0x38
#define  G7_PINMUX_REG_REG_PWR_GPIO2_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_GPIO2_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_GPIO2_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO2_PIN_SEL_EN   0x38
#define  G7_PINMUX_REG_REG_PWR_GPIO2_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_GPIO2_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_GPIO2_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO2_DRI_SEL   0x38
#define  G7_PINMUX_REG_REG_PWR_GPIO2_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_GPIO2_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_GPIO2_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO2_SCT_EN   0x38
#define  G7_PINMUX_REG_REG_PWR_GPIO2_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_GPIO2_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_GPIO2_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO2_OEX_EN   0x38
#define  G7_PINMUX_REG_REG_PWR_GPIO2_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_GPIO2_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_GPIO2_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO3_P_EN   0x3c
#define  G7_PINMUX_REG_REG_PWR_GPIO3_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_GPIO3_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO3_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO3_PU_SEL   0x3c
#define  G7_PINMUX_REG_REG_PWR_GPIO3_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_GPIO3_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_GPIO3_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO3_PIN_SEL_EN   0x3c
#define  G7_PINMUX_REG_REG_PWR_GPIO3_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_GPIO3_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_GPIO3_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO3_DRI_SEL   0x3c
#define  G7_PINMUX_REG_REG_PWR_GPIO3_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_GPIO3_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_GPIO3_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO3_SCT_EN   0x3c
#define  G7_PINMUX_REG_REG_PWR_GPIO3_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_GPIO3_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_GPIO3_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO3_OEX_EN   0x3c
#define  G7_PINMUX_REG_REG_PWR_GPIO3_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_GPIO3_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_GPIO3_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO4_P_EN   0x40
#define  G7_PINMUX_REG_REG_PWR_GPIO4_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_GPIO4_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO4_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO4_PU_SEL   0x40
#define  G7_PINMUX_REG_REG_PWR_GPIO4_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_GPIO4_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_GPIO4_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO4_PIN_SEL_EN   0x40
#define  G7_PINMUX_REG_REG_PWR_GPIO4_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_GPIO4_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_GPIO4_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO4_DRI_SEL   0x40
#define  G7_PINMUX_REG_REG_PWR_GPIO4_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_GPIO4_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_GPIO4_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO4_SCT_EN   0x40
#define  G7_PINMUX_REG_REG_PWR_GPIO4_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_GPIO4_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_GPIO4_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO4_OEX_EN   0x40
#define  G7_PINMUX_REG_REG_PWR_GPIO4_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_GPIO4_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_GPIO4_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO5_P_EN   0x44
#define  G7_PINMUX_REG_REG_PWR_GPIO5_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_GPIO5_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO5_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO5_PU_SEL   0x44
#define  G7_PINMUX_REG_REG_PWR_GPIO5_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_GPIO5_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_GPIO5_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO5_PIN_SEL_EN   0x44
#define  G7_PINMUX_REG_REG_PWR_GPIO5_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_GPIO5_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_GPIO5_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO5_DRI_SEL   0x44
#define  G7_PINMUX_REG_REG_PWR_GPIO5_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_GPIO5_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_GPIO5_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO5_SCT_EN   0x44
#define  G7_PINMUX_REG_REG_PWR_GPIO5_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_GPIO5_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_GPIO5_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO5_OEX_EN   0x44
#define  G7_PINMUX_REG_REG_PWR_GPIO5_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_GPIO5_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_GPIO5_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO6_P_EN   0x48
#define  G7_PINMUX_REG_REG_PWR_GPIO6_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_GPIO6_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO6_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO6_PU_SEL   0x48
#define  G7_PINMUX_REG_REG_PWR_GPIO6_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_GPIO6_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_GPIO6_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO6_PIN_SEL_EN   0x48
#define  G7_PINMUX_REG_REG_PWR_GPIO6_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_GPIO6_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_GPIO6_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO6_DRI_SEL   0x48
#define  G7_PINMUX_REG_REG_PWR_GPIO6_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_GPIO6_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_GPIO6_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_GPIO6_SCT_EN   0x48
#define  G7_PINMUX_REG_REG_PWR_GPIO6_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_GPIO6_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_GPIO6_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_GPIO6_OEX_EN   0x48
#define  G7_PINMUX_REG_REG_PWR_GPIO6_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_GPIO6_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_GPIO6_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_RSTN_P_EN   0x4c
#define  G7_PINMUX_REG_REG_PWR_RSTN_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_PWR_RSTN_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_PWR_RSTN_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_RSTN_PU_SEL   0x4c
#define  G7_PINMUX_REG_REG_PWR_RSTN_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_PWR_RSTN_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_PWR_RSTN_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_RSTN_PIN_SEL_EN   0x4c
#define  G7_PINMUX_REG_REG_PWR_RSTN_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_PWR_RSTN_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_PWR_RSTN_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_RSTN_DRI_SEL   0x4c
#define  G7_PINMUX_REG_REG_PWR_RSTN_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_PWR_RSTN_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_PWR_RSTN_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_PWR_RSTN_SCT_EN   0x4c
#define  G7_PINMUX_REG_REG_PWR_RSTN_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_PWR_RSTN_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_PWR_RSTN_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_PWR_RSTN_OEX_EN   0x4c
#define  G7_PINMUX_REG_REG_PWR_RSTN_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_PWR_RSTN_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_PWR_RSTN_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_P_EN   0x50
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_P_EN_OFFSET 0
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_P_EN_MASK   0x1
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_P_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_PU_SEL   0x50
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_PU_SEL_OFFSET 1
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_PU_SEL_MASK   0x2
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_PU_SEL_BITS   0x1
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_PIN_SEL_EN   0x50
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_PIN_SEL_EN_OFFSET 4
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_PIN_SEL_EN_MASK   0xf0
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_PIN_SEL_EN_BITS   0x4
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_DRI_SEL   0x50
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_DRI_SEL_OFFSET 8
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_DRI_SEL_MASK   0xf00
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_DRI_SEL_BITS   0x4
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_SCT_EN   0x50
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_SCT_EN_OFFSET 12
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_SCT_EN_MASK   0x1000
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_SCT_EN_BITS   0x1
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_OEX_EN   0x50
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_OEX_EN_OFFSET 13
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_OEX_EN_MASK   0x2000
#define  G7_PINMUX_REG_REG_CLK_25M_SEL_OEX_EN_BITS   0x1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_XE   0x54
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_XE_OFFSET 0
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_XE_MASK   0x1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_XE_BITS   0x1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_REF0   0x54
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_REF0_OFFSET 1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_REF0_MASK   0x2
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_REF0_BITS   0x1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_REF1   0x54
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_REF1_OFFSET 2
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_REF1_MASK   0x4
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_REF1_BITS   0x1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_RD0   0x54
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_RD0_OFFSET 3
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_RD0_MASK   0x8
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_RD0_BITS   0x1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_RD1   0x54
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_RD1_OFFSET 4
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_RD1_MASK   0x10
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_RD1_BITS   0x1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS0   0x54
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS0_OFFSET 5
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS0_MASK   0x20
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS0_BITS   0x1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS1   0x54
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS1_OFFSET 6
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS1_MASK   0x40
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS1_BITS   0x1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS2   0x54
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS2_OFFSET 7
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS2_MASK   0x80
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS2_BITS   0x1
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS3   0x54
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS3_OFFSET 8
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS3_MASK   0x100
#define  G7_PINMUX_REG_IO_G6_PWR_XTAL_XIN_DS3_BITS   0x1
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_OE_X   0x54
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_OE_X_OFFSET 9
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_OE_X_MASK   0x200
#define  G7_PINMUX_REG_REG_CLK_25M_OUT_OE_X_BITS   0x1
